SiFive is hiring

Staff RTL Design Engineer - CPU Midcore

Cambridge, England, United KingdomSemiconductor Manufacturing 501-1000 Employees

Sponsorship not specified

This role has closed

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RISC-V inventors founded SiFive — Spun out of UC Berkeley.

$2.5B+ valuation — Achieved in 2021 Series F round.

Google selected SiFive — For next-gen data center processor development.

Intel's Horse Creek platform — Features SiFive P550 RISC-V cores.

Qualcomm Snapdragon Wear — Powered by SiFive RISC-V cores.

Staff RTL Design Engineer - CPU Midcore

Architect and implement new features for industry-leading RISC-V CPU cores using Chisel.
Develop microarchitecture, integrate designs, and optimize for performance, power, and area goals.
Your designs will power next-gen AI, automotive, and mobile applications globally.

ChiselSystemVerilogRISC-VScalaGit

MicroarchitectureRTL DesignCPU ArchitectureSoftware EngineeringASIC Verification

SiFive is no longer accepting applications. Explore similar deep-tech roles you can still apply to.