Last week we reviewed 4 deep-tech roles across 4 disciplines — and every one of them is a software engineer who reasons about custom silicon. PHINIA hires automotive ECU electronics; lowRISC hires a Senior/Principal SE on the OpenTitan / Ibex toolchain; QinetiQ hires an embedded SE interfacing on-board FPGAs; MBDA hires a Linux HPC Architect on bare-metal InfiniBand and RDMA. Same craft. Four different "industry" labels.
The visible market reflects the labels, not the craft. Hardware Engineer = 56 companies / 28,237 engineers. Software Engineer = 89 / 42,450. Embedded Software Engineer = 71 / 38,067. Linux Kernel Engineer = 151 / 61,872. Combined headline: 170,626 engineers across 367 companies if you summed the slugs. But the engineers who actually do this craft — software fluency + silicon-boundary reasoning + UK clearance pathway where the role demands it — number in the low hundreds. The same 200–300 engineers show up across 2–3 of those slugs at once.
Four roles. Four different lookup pools (61,872 / 42,450 / 38,067 / 28,237). Same narrow craft pool: low hundreds.
The signal: Four lookups. One craft. The lookup slug is the wrong unit of measurement — the craft is. Sourcing only the "obvious" slug gives you a third of the addressable pool.
If you're sourcing for any of these 4 roles this quarter, your candidate set lives in 2–3 slugs simultaneously. Search across them, dedupe, and brief the hiring manager on the cross-slug number — not the headline. The candidates you want hop between automotive ECU, open-source silicon, defence FPGA, and HPC infrastructure across a career — they don't sit in one industry bucket.
Microsoft moved CHERIoT capability-based memory-safety research to lowRISC stewardship in Dec 2023; Earl Grey OpenTitan production silicon taped out at TSMC in 2024. GitHub history is portable career signal.
Software Against Silicon — Defence, FPGA-Bordering
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QinetiQ — Senior Embedded Software Engineer, Great Malvern
Embedded SW + bespoke on-board FPGA + UML + rigorous configuration management. Mission-systems engineering, not commercial embedded. SC clearance baseline. Malvern is where Gray and Hilsum invented the first stable LCD (RRE, 1970).
The durable systems language for software-against-silicon. Even the Rust-heavy lowRISC role names C as primary. Sourcing tactic: filter for recent C/C++ commits in Git histories — not job-title C/C++ claims.
FPGA / on-board FPGA interfacing2 of 4 roles
QinetiQ explicit, PHINIA via custom-silicon ECU. The "embedded SW" role and the "hardware" role both write against custom silicon. Filter for FPGA-adjacent CVs even on software-titled roles — widens the cross-slug pool by 30–40%.
Linux3 of 4 roles
Open-source RISC-V silicon engineers run Linux toolchains; defence HPC engineers run Linux. There is no "Windows-shop" version of these roles. Linux distro packaging + kernel-module experience is a fast cross-discipline filter.
UK security clearance (SC + DV)2 of 4 roles
QinetiQ SC baseline, MBDA DV required. Only 8% of either lookup pool sits in Aerospace & Defence — the clearance bar drags from a small slice. Cleared notice periods run 3–6 months: programme-shaped, not market-shaped.
Rust + RISC-V + open-source attributionWatch this space
Explicit in 1 role (lowRISC). The next 5 years of deep-tech systems software will reward engineers with public OSS history + Rust + open-ISA literacy. Microsoft transferring CHERIoT into lowRISC stewardship is the loudest data-point.
When all four of last week's roles map to different slugs but the same craft, the right sourcing search is "engineers who write software against custom hardware" — not "Embedded Software Engineer" or "Hardware Engineer" alone. Each of those slugs surfaces a third of the addressable pool. Cross-slug search surfaces the rest.
An engineer comfortable on the QinetiQ on-board-FPGA boundary is also a viable candidate for the PHINIA ECU role (different industry, same silicon-boundary skill); the MBDA HPC architect with InfiniBand + RDMA + Linux is the same profile that lowRISC's open-source silicon CI/CD pipeline needs. The candidates flow between defence, automotive, hyperscaler, and open-source over a career — they don't sit in one industry bucket.
Build a 3-slug shortlist instead of a single-slug one
1
Pick the trio that brackets the craft. For a defence-cleared embedded role: Embedded Software Engineer + Hardware Engineer + Linux Kernel Engineer. For an open-source toolchain role: Software Engineer + FPGA Engineer + Embedded Systems Engineer.
2
Dedupe by LinkedIn or GitHub. The same 200–300 engineers show up across 2–3 slugs at once. Without dedup you'll triple-count without realising.
3
Brief the hiring manager on the cross-slug deduped number. Not the single-lookup headline. Expect 40–80 candidates instead of 5–10.
4
Filter by silicon proximity, not job title. Recent C/C++ commits, FPGA-interfacing experience, open-source Linux/RISC-V contributions, on-board-hardware bring-up history. The job title is downstream of the craft.
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