Digital Design's Small Door

This week we went deep on a single market: Digital Design Engineering. 23,341 engineers across 26 companies in our talent mapping — that looks healthy, until you look at the crafts sitting right next to it.

Three canonical crafts adjacent to the parent each dwarf it: FPGA Engineer (9,711 engineers · 46 companies), ASIC Engineer (37,443 engineers · 31 companies), Design Verification Engineer (31,392 engineers · 32 companies). The DDE umbrella is a search that narrows you out of the actual pool.

Inside our talent mapping for the parent, 63% of the 23,341 engineers concentrate in Hardware & Semiconductor (14,669 engineers across 18 companies), with Software & Digital Platforms #2 at 28% (6,469 engineers, 5 companies — densely concentrated). And demand is real: 19 companies competing for 25 live Digital Design roles right now — MBDA and Cirrus Logic on three each, plus Fractile, PsiQuantum, SiFive, Apple, Graphcore, Qualcomm and Allegro. The question isn't where — it's which sub-craft.

We read the skills across all 26 parent companies. They point straight at which sub-craft a role really is:

• SystemVerilog — 54% of companies, and RTL Design — 54%. The digital-design core: RTL synthesis and hardware description. Click through to FPGA Engineer or ASIC Engineer for the full market.
• Verilog — 42% and Digital Design — 42%. The naming overlap — a JD leaning on these is inside the umbrella; drill into the sub-craft to source the right pool.
• RTL — 38%. Complements the SystemVerilog+RTL Design pair; look for it alongside DV/UVM in Verification & Test roles.
• ASIC — 35%. The implementation signal: 9 of the 26 parent companies want ASIC engineers, but the /lookup/asic-engineer canonical shows 31 companies. The parent understates the ASIC pool 3.4×.
• Watch this space: match the skill to the canonical sub-craft, click into that craft's own market, and the shortlist stops feeling narrow.

Don't search the umbrella — search the sub-craft that matches the role. "Digital Design Engineer" is a title that narrows you to 26 companies when the actual work spans four canonical markets, three of which have their own /lookup pages with far bigger pools.

Ask the hiring manager one question — is this RTL/verification-heavy, FPGA-configurable, or silicon-implementation? — then let the canonical filter for you: DV/UVM/SystemVerilog verification ⇒ Design Verification Engineer; reconfigurable logic ⇒ FPGA Engineer; silicon implementation ⇒ ASIC Engineer. And don't stop at Hardware & Semiconductor — Software & Digital Platforms holds 6,469 engineers across just 5 companies (28% of the parent pool, densely concentrated) that title-only "hardware" searches skip.

• Parent market numbers & roleSpecs — live /lookup/digital-design-engineer (totalMatches / totalMappedEngineers / roleSpecializations), read 30 Jul 2026.
• Sub-craft markets — live /lookup/fpga-engineer, /lookup/asic-engineer, and /lookup/design-verification-engineer, read 30 Jul 2026.
• Skills Radar — /lookup skillsDemand for digital-design-engineer, read 30 Jul 2026.
• Demand — /lookup activelyCompeting (19 companies / 25 live roles), read 30 Jul 2026 (auto-refreshed on every advert publish via the onJobAdvertPublished trigger and every daily reconcile).
• Shortlist of the week — live pipeline for "Senior Digital Design Engineer (AP)" (scorecardId t3A455QU71qiA714hQbS, 911 evaluated, 404 shortlisted = 87 great-fit + 317 strong-fit), read 30 Jul 2026. Counts only; no candidate data shown.
• Shared data pull for this edition: content-production/data-pulls/2026-07-30-digital-design-engineer-w02.json — the single JSON that all Week 2 surfaces (newsletter, market signals, master advert) read from.